View MAX1280_50216.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1684; Rev 0; 5/00
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
General Description
The MAX1280/MAX1281 12-bit ADCs combine an 8-channel analog-input multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. The MAX1280 operates from a single +4.5V to +5.5V supply; the MAX1281 operates from a single +2.7V to +3.6V supply. Both devices' analog inputs are software configurable for unipolar/bipolar and singleended/pseudo-differential operation. The 4-wire serial interface connects directly to SPITM/QSPITM/MICROWIRETM devices without external logic. A serial strobe output allows direct connection to TMS320-family digital signal processors. The MAX1280/ MAX1281 use an external serial-interface clock to perform successive-approximation analog-to-digital conversions. Both parts feature an internal +2.5V reference and a reference-buffer amplifier with a 1.5% voltageadjustment range. An external reference with a 1V to VDD1 range may also be used. The MAX1280/MAX1281 provide a hard-wired SHDN pin and four software-selectable power modes (normal operation, reduced power, fast power-down, and full power-down). These devices can be programmed to automatically shut down at the end of a conversion or to operate with reduced power. When using the powerdown modes, accessing the serial interface automatically powers up the devices, and the quick turn-on time allows them to be powered down between all conversions. This technique can cut supply current to under 100A at reduced sampling rates. The MAX1280/MAX1281 are available in 20-pin TSSOP packages. These devices are higher-speed versions of the MAX146/MAX147 (for more information, see the respective data sheet).
Features
o 8-Channel Single-Ended or 4-Channel Pseudo-Differential Inputs o Internal Multiplexer and Track/Hold o Single-Supply Operation +4.5V to +5.5V (MAX1280) +2.7V to +3.6V (MAX1281) o Internal +2.5V Reference o 400ksps Sampling Rate (MAX1280) o Low Power 2.5mA (400ksps) 1.3mA (Reduced-Power Mode) 0.9mA (Fast Power-Down Mode) 2A (Full Power-Down) o SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire Serial Interface o Software-Configurable Unipolar or Bipolar Inputs o 20-Pin TSSOP Package
MAX1280/MAX1281
Ordering Information
PART MAX1280BCUP MAX1280BEUP TEMP. RANGE 0C to +70C -40C to +85C PINPACKAGE 20 TSSOP 20 TSSOP INL (LSB) 1 1
Ordering Information continued at end of data sheet.
Pin Configuration
TOP VIEW
CH0 1 CH1 2 CH2 3 CH3 4 CH4 5 CH5 6 CH6 7 CH7 8 COM 9 20 VDD1 19 VDD2 18 SCLK
Applications
Portable Data Logging Data Acquisition Medical Instruments Battery-Powered Instruments Pen Digitizers Process Control
MAX1280 MAX1281
17
CS
16 DIN 15 SSTRB 14 DOUT 13 GND 12 REFADJ 11 REF
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
SHDN 10
TSSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
ABSOLUTE MAXIMUM RATINGS
VDD_ to GND ............................................................ -0.3V to +6V VDD1 to VDD2 ........................................................ -0.3V to +0.3V CH0-CH7, COM to GND.......................... -0.3V to (VDD1 + 0.3V) REF, REFADJ to GND .............................. -0.3V to (VDD1 + 0.3V) Digital Inputs to GND .............................................. -0.3V to +6V Digital Outputs to GND ............................ -0.3V to (VDD2 + 0.3V) Digital Output Sink Current .................................................25mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 7.0mW/C above +70C) .........559mW Operating Temperature Ranges MAX128_BCUP .................................................. 0C to +70C MAX128_BEUP ............................................... -40C to +85C Storage Temperature Range ............................ -60C to +150C Lead Temperature (soldering, 10s) ................................ +300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX1280
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain-Error Temperature Coefficient Channel-to-Channel Offset-Error Matching 0.8 0.1 INL DNL No missing codes over temperature 12 1.0 1.0 6.0 6.0 Bits LSB LSB LSB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk (Note 4) Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle fSCLK 0.5 40 tCONV tACQ 10 <50 6.4 60 2.5 468 s ns ns ps MHz % SINAD THD SFDR IMD fIN1 = 99kHz, fIN2 = 102kHz fIN = 200kHz, VIN = 2.5Vp-p -3dB point SINAD > 68dB Up to the 5th harmonic 70 -81 80 76 -78 6 350 dB dB dB dB dB MHz kHz
2
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS--MAX1280 (continued)
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS Unipolar, VCOM = 0 VCH_ Bipolar, VCOM or VCH_ = VREF/2, referenced to COM or CH_ On/off leakage current, VCH_ = 0 or VDD1 0.001 18 VREF TA = +25C 2.480 2.500 30 TC VREF 0 to 1mA output load 4.7 0.01 1.22 For small adjustments, from 1.22V To power down the internal reference 1.4 2.05 1.0 200 VDD1 + 50mV 350 320 5 3.0 0.8 0.2 VIN = 0 or VDD2 15 ISINK = 5mA ISOURCE = 1mA CS = 5V CS = 5V 15 4 10 0.4 1 A mA 100 VDD1 15 0.1 2.0 10 10 2.520 MIN TYP MAX VREF VREF/2 1 V A pF V mA ppm/C mV/mA F F V mV V V/V UNITS ANALOG INPUTS (CH7-CH0, COM) Input Voltage Range, SingleEnded and Differential (Note 6) Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Short-Circuit Current REF Output Temperature Coefficient Load Regulation (Note 7) Capacitive Bypass at REF Capacitive Bypass at REFADJ REFADJ Output Voltage REFADJ Input Range REFADJ Buffer Disable Threshold Buffer Voltage Gain EXTERNAL REFERENCE (Reference buffer disabled, reference applied to REF) REF Input Voltage Range (Note 8) VREF = 2.500V, fSCLK = 6.4MHz REF Input Current DIGITAL INPUTS (DIN, SCLK, CS, SHDN) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Input Capacitance DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance VOL VOH IL COUT V V A pF VINH VINL VHYST IIN CIN V V V A pF VREF = 2.500V, fSCLK = 0 In power-down, fSCLK = 0 V
MAX1280/MAX1281
_______________________________________________________________________________________
3
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
ELECTRICAL CHARACTERISTICS--MAX1280 (continued)
(VDD1 = VDD2 = +4.5V to +5.5V, COM = GND, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER POWER SUPPLY Positive Supply Voltage (Note 9) VDD1, VDD2 Operating mode (Note 10) Supply Current Supply Current Power-Supply Rejection PSR IVDD1 + IVDD2 VDD1 = VDD2 = 5.5V Reduced-power mode (Note 11) Fast power-down (Note 11) Full power-down (Note 11) VDD1 = VDD2 = 5V 10%, midscale input 4.5 2.5 1.3 0.9 2 0.5 5.5 4.0 2.0 1.5 10 2.0 A mV mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS--MAX1281
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain-Error Temperature Coefficient Channel-to-Channel OffsetError Matching 1.6 0.2 INL DNL No missing codes over temperature 12 1.0 1.0 6.0 6.0 Bits LSB LSB LSB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode) Signal-to-Noise plus Distortion Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk (Note 4) Full-Power Bandwidth Full-Linear Bandwidth SINAD THD SFDR IMD fIN1 = 73kHz, fIN2 = 77kHz fIN = 150kHz, VIN = 2.5Vp-p -3dB point SINAD > 68dB Up to the 5th harmonic 70 -81 80 76 -78 3 250 dB dB dB dB dB MHz kHz
4
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS--MAX1281 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CONVERSION RATE Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Serial Clock Frequency Duty Cycle ANALOG INPUTS (CH7-CH0, COM) Input Voltage Range, SingleEnded and Differential (Note 6) Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Short-Circuit Current REF Output Temperature Coefficient Load Regulation (Note 7) Capacitive Bypass at REF Capacitive Bypass at REFADJ REFADJ Output Voltage REFADJ Input Range REFADJ Buffer Disable Threshold Buffer Voltage Gain EXTERNAL REFERENCE (Reference buffer disabled, reference applied to REF) REF Input Voltage Range (Note 8) VREF = 2.500V, fSCLK = 4.8MHz REF Input Current DIGITAL INPUTS (DIN, SCLK, CS, SHDN) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Input Capacitance VINH VINL VHYST IIN CIN VIN = 0 or VDD2 15 0.2 1 2.0 0.8 V V V A pF VREF = 2.500V, fSCLK = 0 In power-down, fSCLK = 0 1.0 200 VDD1 + 50mV 350 320 5 A V For small adjustments, from 1.22V To power down the internal reference 1.4 2.05 TC VREF 0 to 0.75mA output load 4.7 0.01 1.22 100 VDD1 - 1 VREF TA = +25C 2.480 2.500 15 15 0.1 2.0 10 10 2.520 V mA ppm/C mV/mA F F V mV V V/V Unipolar, VCOM = 0 VCH_ Bipolar, VCOM or VCH_ = VREF/2, referenced to COM or CH_ On/off leakage current, VCH_ = 0 or AVDD 0.001 18 VREF VREF/2 1 V A pF fSCLK Normal operating mode 0.5 40 tCONV tACQ Normal operating mode Normal operating mode 10 <50 4.8 60 3.3 625 s ns ns ps MHz % SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1280/MAX1281
_______________________________________________________________________________________
5
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
ELECTRICAL CHARACTERISTICS--MAX1281 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external +2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER SUPPLY Positive Supply Voltage (Note 9) VDD1, VDD2 Operating mode (Note 10) Supply Current IVDD1 + IVDD2 PSR Reduced-power mode (Note 11) VDD1 = VDD2 = 3.6V Fast power-down (Note 11) Full power-down (Note 11) VDD1 = VDD2 = 2.7V to 3.6V, midscale input 2.7 2.5 1.3 0.9 2 0.5 3.6 3.5 2.0 1.5 10 2.0 A mV mA V SYMBOL VOL VOH IL COUT ISINK = 5mA ISOURCE = 0.5mA CS = 3V CS = 3V 15 VDD2 - 0.5V 10 CONDITIONS MIN TYP MAX 0.4 UNITS V V A pF DIGITAL OUTPUTS (DOUT, SSTRB)
Power-Supply Rejection
TIMING CHARACTERISTICS--MAX1280
(Figures 1, 2, 6, 7; VDD1 = VDD2 = +4.5V to +5.5V; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Setup DIN to SCLK Hold CS Fall to SCLK Rise Setup SCLK Rise to CS Rise Hold SCLK Rise to CS Fall Ignore CS Rise to SCLK Rise Ignore SCLK Rise to DOUT Hold SCLK Rise to SSTRB Hold SCLK Rise to DOUT Valid SCLK Rise to SSTRB Valid CS Rise to DOUT Disable CS Rise to SSTRB Disable CS Fall to DOUT Enable CS Fall to SSTRB Enable CS Pulse Width High SYMBOL tCP tCH tCL tDS tDH tCSS tCSH tCSO tCS1 tDOH tSTH tDOV tSTV tDOD tSTD tDOE tSTE tCSW CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF 100 10 10 CONDITIONS MIN 156 62 62 35 0 35 0 35 35 10 10 20 20 80 80 65 65 65 65 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS--MAX1281
(Figures 1, 2, 6, 7; VDD1 = VDD2 = +2.7V to +3.6V; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SCLK Period SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Setup DIN to SCLK Hold CS Fall to SCLK Rise Setup SCLK Rise to CS Rise Hold SCLK Rise to CS Fall ignore CS Rise to SCLK Rise Ignore SCLK Rise to DOUT Hold SCLK Rise to SSTRB Hold SCLK Rise to DOUT Valid SCLK Rise to SSTRB Valid CS Rise to DOUT Disable CS Rise to SSTRB Disable CS Fall to DOUT Enable CS Fall to SSTRB Enable CS Pulse Width High SYMBOL tCP tCH tCL tDS tDH tCSS tCSH tCSO tCS1 tDOH tSTH tDOV tSTV tDOD tSTD tDOE tSTE tCSW CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF 100 13 13 CONDITIONS MIN 208 83 83 45 0 45 0 45 45 13 1 20 20 100 100 85 85 85 85 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX1280/MAX1281
Note 1: MAX1280 tested at VDD1 = VDD2 = +5V, MAX1281 tested at VDD1 = VDD2 = +3V; COM = GND; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. Note 3: Offset nulled. Note 4: Ground "on" channel; sine wave applied to all "off" channels. Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The absolute voltage range for the analog inputs (CH7-CH0, and COM) is from GND to VDD1. Note 7: External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is a result of production test limitations. Note 8: ADC performance is limited by the converter's noise floor, typically 300Vp-p. Note 9: Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) to VDD1(MAX) = VDD2(MAX). For operations beyond this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory. Note 10: AIN = midscale. Unipolar mode. MAX1280 tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 6.4MHz, 0 to 5V. MAX1281 tested with same loads, fSCLK = 4.8MHz, 0 to 3V. DOUT = FFF hex. Note 11: SCLK = DIN = GND, CS = VDD1.
_______________________________________________________________________________________
7
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Typical Operating Characteristics
(MAX1280: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1281: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7F capacitor at REF, 0.01F capacitor at REFADJ, TA = +25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1280/1-01
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1280/1-02
SUPPLY CURRENT vs. SUPPLY VOLTAGE (CONVERTING)
MAX1280/1-03
0.5 0.4 0.3
0.6 0.4 0.2 DNL (LSB) 0 -0.2
3.5
INL (LSB)
0.2 0.1 0 -0.1 -0.2 -0.3 0 500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL OUTPUT CODE
SUPPLY CURRENT (mA) 0 500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL OUTPUT CODE
3.0
2.5
2.0 -0.4 -0.6 1.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX1280/1-04
SUPPLY CURRENT vs. SUPPLY VOLTAGE (STATIC)
MAX1280/1-05
SUPPLY CURRENT vs. TEMPERATURE (STATIC)
MAX1280/1-06
3.2 3.0 SUPPLY CURRENT (mA) 2.8 2.6 2.4 MAX1281 2.2 2.0 -40 -20 0 20 40 60 80 MAX1280
2.5 NORMAL OPERATION (PD1 = PD0 = 1)
2.5 MAX1280 (PD1 = 1, PD0 = 1) MAX1281 (PD1 = 1, PD0 = 1) 1.5 MAX1280 (PD1 = 1, PD0 = 0) MAX1281 (PD1 = 1, PD0 = 0)
2.0 SUPPLY CURRENT (mA)
2.0 SUPPLY CURRENT (mA)
1.5
REDP (PD1 = 1, PD0 = 0)
1.0 FASTDP (PD1 = 0, PD0 = 1) 0.5
1.0
0.5
MAX1280 (PD1 = 0, PD0 = 1) MAX1281 (PD1 = 0, PD0 = 1)
0 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TEMPERATURE (C) SUPPLY VOLTAGE (V)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1280/1-07
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX1280/1-08
REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1280/1-09
5 (PD1 = PD0 = 0) SHUTDOWN CURRENT (A) 4
2.5 (PD1 = PD0 = 0) SHUTDOWN CURRENT (A) 2.0 MAX1280
2.5005
2.5003 REFERENCE VOLTAGE (V)
3
1.5 MAX1281
2.5001
2
1.0
2.4999
1
0.5
2.4997
0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
2.4995 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
Typical Operating Characteristics (continued)
(MAX1280: VDD1 = VDD2 = 5.0V, fSCLK = 6.4MHz; MAX1281: VDD1 = VDD2 = 3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7F capacitor at REF, 0.01F capacitor at REFADJ, TA = +25C, unless otherwise noted.)
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1280/1-10
MAX1280/MAX1281
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1280/1-11
OFFSET ERROR vs. TEMPERATURE
MAX1280/1-12
2.5002 2.5000 MAX1280 REFERENCE VOLTAGE (V) 2.4998 2.4996 2.4994 2.4992 MAX1281
0
0.5 0 OFFSET ERROR (LSB) -0.5 -1.0 -1.5 -2.0 -2.5
-0.5 OFFSET ERROR (LSB)
-1.0
-1.5
-2.0 2.4990 2.4988 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) -2.5 2.7 3.0 VDD (V) 3.3 3.6
-40
-15
10
35
60
85
TEMPERATURE (C)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1280/1-13
GAIN ERROR vs. TEMPERATURE
MAX1281 0 GAIN ERROR (LSB)
MAX1280/1-14
1
0.5
0 GAIN ERROR (LSB) -0.5
-1
-1.0
-2
-1.5
-3 2.7 3.0 VDD (V) 3.3 3.6
-2.0 -40 -15 10 35 60 85 TEMPERATURE (C)
_______________________________________________________________________________________
9
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Pin Description
PIN 1-8 9 10 NAME CH0-CH7 COM SHDN Sampling Analog Inputs Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be stable to 0.5LSB. Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2A (typ). Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the reference buffer provides a +2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD1. Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD1. Analog and Digital Ground Serial Data Output. Data is clocked out at SCLK's rising edge. High impedance when CS is high. Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high. Serial Data Input. Data is clocked in at SCLK's rising edge. Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT and SSTRB are high impedance. Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty cycle must be 40% to 60%.) Positive Supply Voltage Positive Supply Voltage FUNCTION
11
REF
12 13 14 15 16 17 18 19 20
REFADJ GND DOUT SSTRB DIN CS SCLK VDD2 VDD1
VDD2
VDD2 6k DOUT CLOAD 20pF GND a) VOH to High-Z DOUT CLOAD 20pF GND b) VOL to High-Z
DOUT CLOAD 20pF GND a) High-Z to VOH and VOL to VOH
DOUT
6k
6k
CLOAD 20pF GND b) High-Z to VOL and VOH to VOL
6k
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
10
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
Detailed Description
The MAX1280/MAX1281 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible serial interface provides easy interface to microprocessors (Ps). Figure 3 shows a functional diagram of the MAX1280/MAX1281. in order to maintain 0.5LSB accuracy. Assuming a sinusoidal signal at IN-, the input voltage is determined by: IN- = VIN- sin(2ft) The maximum voltage variation is determined by: max dIN1LSB VREF = VIN- 2f = 12 dt t CONV 2 t CONV
MAX1280/MAX1281
(
)
(
)
Pseudo-Differential Input
The equivalent input circuit of Figure 4 shows the MAX1280/MAX1281's input architecture, which is composed of a T/H, input multiplexer, input comparator, switched-capacitor DAC, and reference. In single-ended mode, the positive input (IN+) is connected to the selected input channel and the negative input (IN-) is set to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels according to Tables 2 and 3. The MAX1280/MAX1281 input configuration is pseudodifferential in that only the signal at IN+ is sampled. The return side (IN-) is connected to the sampling capacitor while converting and must remain stable within 0.5LSB (0.1LSB for best results) with respect to GND during a conversion. If a varying signal is applied to the selected IN-, its amplitude and frequency must be limited to maintain accuracy. The following equations determine the relationship between the maximum signal amplitude and its frequency
A 650mVp-p 60Hz signal at IN- will generate 0.5LSB of error when using a +2.5V reference voltage and a 2.5s conversion time (15/fSCLK). When a DC reference voltage is used at IN-, connect a 0.1F capacitor to GND to minimize noise at the input. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from IN+ to IN-. This unbalances node ZERO at the comparator's input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to V DD1 /2 within the limits of 12-bit resolution. This action is equivalent to transferring a 12pF x (VIN+ - VIN-) charge from CHOLD to the binaryweighted capacitive DAC, which in turn forms a digital representation of the analog input signal.
CS SCLK DIN SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
17 18 16 10 1 2 3 4 5 6 7 8 9 +1.22V REFERENCE 17k INPUT SHIFT REGISTER INT CLOCK CONTROL LOGIC OUTPUT SHIFT REGISTER ANALOG INPUT MUX T/H CLOCK IN 12-BIT SAR ADC OUT REF A 2.05* 14 15 DOUT SSTRB
GND REF CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
20 19 13 +2.500V VDD1 VDD2 GND
CAPACITATIVE DAC CHOLD 12pF
INPUT MUX
ZERO RIN 800
COMPARATOR
CSWITCH* 6pF HOLD
CH8
TRACK AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. VDD1/2
REFADJ 12 REF 11
MAX1280 MAX1281
SINGLE-ENDED MODE: IN+ = CH0-CH7, IN- = COM. PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7. *INCLUDES ALL INPUT PARASITICS
Figure 3. Functional Diagram
Figure 4. Equivalent Input Circuit 11
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Track/Hold
The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM and the converter converts the "+" input. If the converter is set up for differential inputs, the difference of [(IN+) - (IN-)] is converted. At the end of the conversion, the positive input connects back to IN+ and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal and is also the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ = 9 (RS + RIN) 12pF where RIN = 800, RS = the source impedance of the input signal; tACQ is never less than 468ns (MAX1280) or 625ns (MAX1281). Note that source impedances below 2k do not significantly affect the ADC's AC performance.
Input Bandwidth
The ADC's input tracking circuitry has a 6MHz (MAX1280) or 3MHz (MAX1281) small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, antialias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog input to VDD1 and GND, allow the channel input pins to swing from GND - 0.3V to VDD1 + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD1 by more than 50mV or be lower than GND by 50mV. If the analog input exceeds 50mV beyond the supplies, do not allow the input current to exceed 2mA.
Quick Look
To quickly evaluate the MAX1280/MAX1281's analog performance, use the circuit of Figure 5. The MAX1280/ MAX1281 require a control byte to be written to DIN before each conversion. Connecting DIN to VDD2 feeds in control bytes of $FF (HEX), which trigger singleended unipolar conversions on CH7 without powering down between conversions. The SSTRB output pulses
OSCILLOSCOPE
0V TO 2.500V ANALOG INPUT 0.01F
MAX1280 MAX1281
CH7
VDD1 VDD2 GND COM CS
+3V or +5V 0.1F 10F
SCLK
SSTRB DOUT* TO VDD2 EXTERNAL CLOCK
REFADJ 0.01F 2.5V 4.7F REF
SCLK DIN DOUT SSTRB SHDN TO VDD2 CH1 CH2 CH3 CH4
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
Figure 5. Quick-Look Circuit 12 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
CS
tACQ SCLK 1 4 8 9 12 16 20 24
DIN
SEL SEL SEL UNI/ SGL/ PD1 PD0 2 1 0 BIP DIF START
SSTRB
HIGH-Z
HIGH-Z
RB1 HIGH-Z DOUT ACQUISITION IDLE
RB2
RB3 HIGH-Z
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 IDLE
CONVERSION
Figure 6. Single-Conversion Timing
high for one clock period before the MSB of the 12-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence of bits from DOUT. A total of 16 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs typically occur 20ns after the rising edge of SCLK.
clock frequency from 500kHz to 6.4MHz (MAX1280) or 4.8MHz (MAX1281). 1) Set up the control byte and call it TB1. TB1 should be of the format 1XXXXXXX binary, where the Xs denote the particular channel, selected conversion mode, and power mode. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3. 6) Pull CS high. Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion, padded with three leading zeros and one trailing zero. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120s. Digital Output In unipolar input mode, the output is straight binary (Figure 14). For bipolar input mode, the output is two's complement (Figure 15). Data is clocked out on the rising edge of SCLK in MSB-first format.
13
Starting a Conversion
Start a conversion by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1280/MAX1281's internal shift register. After CS falls, the first arriving logic "1" bit defines the control byte's MSB. Until this first "start" bit arrives, any number of logic "0" bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The MAX1280/MAX1281 are compatible with SPI/QSPI and MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 12-bit conversion result). See Figure 17 for MAX1280/MAX1281 QSPI connections. Simple Software Interface Make sure the CPU's serial interface runs in master mode, so the CPU generates the serial clock. Choose a
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Table 1. Control-Byte Format
BIT 7 (MSB) START BIT 7 (MSB) 6 5 4 3 BIT 6 SEL2 NAME START SEL2 SEL1 SEL0 UNI/BIP BIT 5 SEL1 BIT 4 SEL0 BIT 3 UNI/BIP DESCRIPTION The first logic "1" bit after CS goes low defines the beginning of the control byte. These three bits select which of the eight channels are used for the conversion (Tables 2 and 3). BIT 2 SGL/DIF BIT 1 PD1 BIT 0 (LSB) PD0
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the differential signal can range from -VREF/2 to +VREF/2. 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2 and 3). Select operating mode. PD1 PD0 Mode 0 0 Full power-down 0 1 Fast power-down 1 0 Reduced Power 1 1 Normal Operation
2
SGL/DIF
1 0 (LSB)
PD1 PD0
Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 + + + + CH0 + CH1 CH2 + + + CH3 CH4 CH5 CH6 CH7 COM - - - - - - - -
Table 3. Channel Selection in Psuedo-Differential Mode (SGL/DIF = 0)
SEL2 0 0 0 0 1 1 1 1 14 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 - + - + - + - + CH0 + CH1 - + - + - + - CH2 CH3 CH4 CH5 CH6 CH7
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
CS tCSW tCSS tCSO SCLK tDS tDH DIN tDOH tDOV tDOE DOUT tSTH tSTV tDOD tCL tCH tCP tCSH tCS1
tSTE SSTRB
tSTD
Figure 7. Detailed Serial-Interface Timing
Serial Clock The external serial clock not only shifts data in and out, but also drives the analog-to-digital conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approximation bit decisions are made and appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). SSTRB and DOUT go into a high-impedance state when CS goes high; after the next CS rising edge, SSTRB outputs a logic low. Figure 7 shows the detailed serial-interface timing. The conversion must complete in 120s or less, or droop on the sample-and-hold capacitors may degrade conversion results. Data Framing The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on SCLK's falling edge after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as follows: The first high bit clocked into DIN with CS low any time the converter is idle, e.g., after VDD1 and VDD2 are applied. OR The first high bit clocked into DIN after bit 6 of a conversion in progress is clocked onto the DOUT pin. Once a start bit has been recognized, the current conversion may only be terminated by pulling SHDN low.
The fastest the MAX1280/MAX1281 can run with CS held low between conversions is 16 clocks per conversion. Figure 8 shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles. If CS is tied low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros.
Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX1280/MAX1281 in normal operating mode, ready to convert with SSTRB = low. The MAX1280/MAX1281 require 10s to reset after the power supplies stabilize; no conversions should be initiated during this time. If CS is low, the first logic 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros. Additionally, wait for the reference to stabilize when using the internal reference.
Power Modes
You can save power by placing the converter in one of the two low-current operating modes or in full powerdown between conversions. Select the power mode through bit 1 and bit 0 of the DIN control byte (Tables 1 and 4), or force the converter into hardware shutdown by driving SHDN to GND. The software power-down modes take effect after the conversion is completed; SHDN overrides any software power mode and immediately stops any conversion in
15
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
CS
DIN
S
CONTROL BYTE 0
S
CONTROL BYTE 1
S
CONTROL BYTE 2
S
ETC
1 SCLK
8
12
16 1
5
8
12
16 1
5
8
12
16 1
5
DOUT
HIGH-Z
B11
B6 CONVERSION RESULT 0
B0
B11
B6 CONVERSION RESULT 1
B0
B11
B6
SSTRB
HIGH-Z
Figure 8. Continuous 16-Clock/Conversion Timing
Table 4. Software-Controlled Power Modes
TOTAL SUPPLY CURRENT PD1/PD0 MODE CONVERTING 00 01 10 11 Full Power-Down (FULLPD) Fast Power-Down (FASTPD) Reduced-Power Mode (REDPD) Operating Mode 2.5mA 2.5mA 2.5mA 2.5mA AFTER CONVERSION 2A 0.9mA 1.3mA 2.0mA CIRCUIT SECTIONS* INPUT COMPARATOR Off Reduced Power Reduced Power Full Power REFERENCE Off On On On
*Circuit operation between conversions; during conversion, all circuits are fully powered up.
progress. In software power-down mode, the serial interface remains active, waiting for a new control byte to start conversion and switch to full-power mode. Once the conversion is completed, the device goes into the programmed power mode until a new control byte is written. The power-up delay is dependent on the power-down state. Software low-power modes will be able to start conversion immediately when running at decreased clock rates (see Power-Down Sequencing). During power-on reset, when exiting software full power-down mode or exiting hardware shutdown, the device goes immediately into full-power mode and is ready to convert after 2s when using an external reference. When using the internal reference, wait for the typical power16
up delay from a full power-down (software or hardware), as shown in Figure 9. Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. When software shutdown is asserted, the ADC completes the conversion in progress and powers down into the specified lowquiescent-current state (2A, 0.9mA, or 1.3mA). The first logic 1 on DIN is interpreted as a start bit and puts the MAX1280/MAX1281 into their full-power mode. Following the start bit, the data input word or control byte also determines the next power-down state. For example, if the DIN word contains PD1 = 0 and PD0 = 1, a 0.9mA power-down starts after the conversion.
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
Table 4 details the four power modes with the corresponding supply current and operating sections. For data rates achievable in software power-down modes, see Power-Down Sequencing. Hardware Power-Down Pulling SHDN low places the converter in hardware power-down. Unlike software power-down mode, the conversion is terminated immediately. When returning to normal operation from SHDN with an external reference, the MAX1280/MAX1281 can be considered fully powered-up within 2s of actively pulling SHDN high. When using the internal reference, the conversion should be initiated only after the reference has settled; its recovery time depends on the external bypass capacitors and shutdown duration. less than maximum sample rates. Figures 10 and 11 show the average supply current as a function of the sampling rate. Using Full Power-Down Mode Full power-down mode (FULLPD) achieves the lowest power consumption at up to 1000 conversions per channel per second. Figure 10a shows the MAX1281's power consumption for 1- or 8-channel conversions using full power-down mode (PD1 = PD0 = 0), with the internal reference and the maximum clock speed. A 0.01F bypass capacitor plus the internal 17k reference resistor at REFADJ forms an RC filter with a 200s time constant. To achieve full 12-bit accuracy, 10 time constants or 2ms are required after power-up if the bypass capacitor is fully discharged between conversions. Waiting this 2ms in FASTPD mode or reducedpower mode (REDP) instead of full power-down mode can further reduce power consumption. This is achieved by using the sequence shown in Figure 12a. Figure 10b shows the MAX1281's power consumption for 1- or 8-channel conversions using FULLPD mode (PD1 = PD0 = 0), an external reference, and the maximum clock speed. One dummy conversion to power-up the device is needed, but no wait-time is necessary to start the second conversion, thereby achieving lower power consumption at up to the full sampling rate. Using Fast Power-Down and Reduced-Power Modes FASTPD and REDP modes achieve the lowest power consumption at speeds close to the maximum sample rate. Figure 11 shows the MAX1281's power consumption in FASTPD mode (PD1 = 0, PD0 = 1), REDP mode (PD1 = 1, PD0 = 0), and (for comparison) normal operating mode (PD = 1, PD0 = 1). The figure shows
10,000 MAX1281 VDD1 = VDD2 = 3.0V CLOAD = 20pF CODE = 101010000000 100 MAX1281 VDD1 = VDD2 = 3.0V CLOAD = 20pF CODE = 101010000000 8 CHANNELS 100 1 CHANNEL 10
MAX1280/MAX1281
Power-Down Sequencing
The MAX1280/MAX1281's automatic power-down modes can save considerable power when operating at
1.50 REFERENCE POWER-UP DELAY (ms) 1.25 1.00 0.75 0.50 0.25 0 0.0001
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (s)
Figure 9. Reference Power-Up Delay vs. Time in Shutdown
1000
SUPPLY CURRENT (A)
8 CHANNELS 10 1 CHANNEL
SUPPLY CURRENT (A)
1000
1 0.1 1 10 100 1k 10k SAMPLING RATE (sps)
1 1 10 100 1k 10k 100k SAMPLING RATE (sps)
Figure 10a. Average Supply Current vs. Sample Rate (Using FULLPD and Internal Reference)
Figure 10b. Average Supply Current vs. Sampling Rate (Using FULLPD and External Reference) 17
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
power consumption using the specified power-down mode, with the internal reference and the maximum clock speed. The clock speed in FASTPD or REDP should be limited to 4.8MHz for the MAX1280/ MAX1281. FULLPD mode may provide increased power
2.5 NORMAL OPERATION SUPPLY CURRENT (mA) 2.0 REDP FASTPD 1.5
savings in applications where the MAX1280/ MAX1281 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required.
Internal and External References
The MAX1280/MAX1281 can be used with an internal or external reference. An external reference can be connected directly at REF or at the REFADJ pin. An internal buffer is designed to provide 2.5V at REF for both the MAX1280/MAX1281. The internally trimmed 1.22V reference is buffered with a gain of +2.05V/V. Internal Reference The MAX1280/MAX1281's full-scale range with the internal reference is 2.5V for unipolar inputs and 1.25V for bipolar inputs. The internal reference voltage is adjustable to 100mV with the circuit of Figure 13.
1.0 MAX1281, VDD1 = VDD2 = 3.0V CLOAD = 20pF CODE = 101010000000 0 50 100 150 200 250 300 350
0.5
SAMPLING RATE (sps)
Figure 11. Average Supply Current vs. Sampling Rate (Using REPD, FASTPD, and Normal Operation and Internal Reference)
External Reference An external reference can be placed at either the input (REFADJ) or the output (REF) of the internal referencebuffer amplifier. The REFADJ input impedance is typically 17k. At REF, the DC input resistance is a minimum of
WAIT 2ms (10 x RC)
1 DIN FULLPD
00
1 REDP
10
1 FULLPD 1.22V
00
1
1.22V RE FADJ 0V 2.5V REF 0V IVDD1 + IVDD2 2.5mA 0mA
DUMMY CONVERSION
= RC = 17k x 0.01F
2.5V
2.5mA 1.3mA OR 0.9mA
2.5mA 0mA
Figure 12a. Full Power-Down Timing
1 DIN REDPD
10
1 REDP
10
1 FASTPD
01
REF
2.5V (ALWAYS ON) 2.5mA 2.5mA 0.9mA 0.9mA 2.5mA 1.3mA
IVDD1 + IVDD2
Figure 12b. Reduced-Power/Fast Power-Down Timing 18 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
+3.3V
OUTPUT CODE
24k MAX1281 510k 100k 12 0.01F REFADJ
000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 011 . . . 111 011 . . . 110 FS = VREF + VCOM 2 ZS = COM -FS = -VREF + VCOM 2 V 1LSB = REF 4096
Figure 13. MAX1281 Reference-Adjust Circuit
OUTPUT CODE FULL-SCALE TRANSITION
111 . . . 101
100 . . . 001 100 . . . 000 - FS COM* INPUT VOLTAGE (LSB) *VCOM VREF / 2 FS = VREF + VCOM ZS = VCOM V 1LSB = REF 4096 +FS - 1LSB
11 . . . 111 11 . . . 110 11 . . . 101
Figure 15. Bipolar Transfer Function, Full Scale (FS) = VREF / 2 + VCOM, Zero Scale (ZS) = VCOM
00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 01 (COM) 2 3 INPUT VOLTAGE (LSB)
tions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = 610V for unipolar and bipolar operation.
Layout, Grounding, and Bypassing
FS FS - 3/2LSB
Figure 14. Unipolar Transfer Function, Full Scale (FS) = VREF + VCOM, Zero Scale (ZS) = VCOM
18k. During conversion, an external reference at REF must deliver up to 350A DC load current and have 10 or less output impedance. If the reference has a higher output impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor. Using the REFADJ input makes buffering the external reference unnecessary. To use the direct REF input, disable the internal buffer by connecting REFADJ to VDD1.
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar and bipolar modes. Figure 14 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 15 shows the bipolar I/O transfer function. Code transi-
For best performance, use printed circuit boards; wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 16 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at GND. Connect all analog grounds to the star ground. Connect the digital system ground to star ground at this point only. For lowest-noise operation, the ground return to the star ground's power supply should be low impedance and as short as possible. High-frequency noise in the VDD1 power supply may affect the high-speed comparator in the ADC. Bypass the supply to the star ground with 0.1F and 10F capacitors, located close to pin 20 of the MAX1280/ MAX1281. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10 resistor can be connected as a lowpass filter (Figure 16).
______________________________________________________________________________________
19
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
Table 5. Full Scale and Zero Scale
UNIPOLAR MODE Full Scale VREF + VCOM Zero Scale COM Positive Full Scale VREF / 2 + VCOM BIPOLAR MODE Zero Scale VCOM Negative Full Scale -VREF / 2 + VCOM
connected with the MAX1280/MAX1281's SCLK input.
SUPPLIES VDD1 GND VDD2
R* = 10
VDD1
GND
COM
VDD2
VDD
DGND
MAX1280 MAX1281
*OPTIONAL
DIGITAL CIRCUITRY
Figure 16. Power-Supply Grounding Connection
2) The MAX1280/MAX1281's CS pin is driven low by the TMS320's XF_ I/O port to enable data to be clocked into the MAX1280/MAX1281's DIN pin. 3) An 8-bit word (1XXXXX11) should be written to the MAX1280/MAX1281 to initiate a conversion and place the device into normal operating mode. See Table 1 to select the proper XXXXX bit values for your specific application. 4) The MAX1280/MAX1281's SSTRB output is monitored through the TMS320's FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX1280/MAX1281. 5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) Pull CS high to disable the MAX1280/MAX1281 until the next conversion is initiated.
High-Speed Digital Interfacing with QSPI
The MAX1280/MAX1281 can interface with QSPI using the circuit in Figure 17 (fSCLK = 4.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own microsequencer.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1280/MAX1281 are measured using the endpoint method.
TMS320LC3x Interface
Figure 18 shows an application circuit that interfaces the MAX1280/MAX1281 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 19. Use the following steps to initiate a conversion in the MAX1280/MAX1281 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and with CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
20
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
+3V OR +5V
+3V OR +5V
1 2 3
CH0 CH1 CH2 CH3 MAX1280 CH4 CH5 CH6 CH7 COM
VDD1 20 VDD2 19 SCLK 18 CS 17 DIN 16 SSTRB 15 DOUT 14 GND 13 REFADJ 12 REF 11
0.1F
10F (POWER SUPPLIES) SCK PCS0 MOSI
ANALOG INPUTS
4 5 6 7 8 9 VDD1
MAX1281
MC683XX
MISO
10 SHDN
4.7F
0.01F
(GND)
Figure 17. QSPI Connections
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, Signal-to-noise ratio (SNR) is the ratio of fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits):
MAX1280 MAX1281
DIN DOUT SSTRB
XF CLKX
CS SCLK
TMS320LC3x
CLKR DX DR FSR
SNR = (6.02 N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise ratio plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals. SINAD (dB) = 20 log (SignalRMS / NoiseRMS)
Figure 18. MAX1280/MAX1281-to-TMS320 Serial Interface
Aperture Delay
Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken.
______________________________________________________________________________________
21
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
CS
SCLK START SEL2 SEL1 SEL0 UNI/BIP SGI/DIF PD1 PD0 HIGH IMPEDANCE MSB B10 B1 B0 HIGH IMPEDANCE
DIN SSTRB DOUT
Figure 19. MAX1280/MAX1281-to-TMS320 Serial Interface
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02
Ordering Information (continued)
PART MAX1281BCUP MAX1281BEUP TEMP. RANGE 0C to +70C -40C to +85C PINPACKAGE 20 TSSOP 20 TSSOP INL (LSB) 1 1
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:
Typical Operating Circuit
+5V OR +3V CH0 VDD1 VDD2 VDD 0.1F
2 2 2 2 2 V2 + V3 + V4 + V4 + V5 THD = 20 x log V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics, respectively.
0 TO +2.5V ANALOG INPUTS
MAX1280 GND MAX1281
CH8 REF COM CS SCLK DIN REFADJ DOUT SSTRB SHDN I/O
CPU
4.7F
SCK (SK) MOSI (SO) MISO (SI) VSS
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
0.01F
___________________Chip Information
TRANSISTOR COUNT: 4286 PROCESS: BiCMOS
22
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
________________________________________________________Package Information
TSSOP.EPS
MAX1280/MAX1281
______________________________________________________________________________________
23
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference
MAX1280/MAX1281
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX1280

	To Download MAX1280 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .